Ion-implanted junction field effect transistors (hereinafter termed I.sup.2 JFETs) typically contain a buried (ion-implanted) channel region which bridges respective source and drain regions of the JFET and the conductive properties of which are controlled by modulation of the space-charge region formed with the adjoining top gate and bottom gate regions. The device structure of an exemplary P-channel I.sup.2 JFET is diagrammatically shown in cross-section in FIG. 1 as comprising a semiconductor (e.g. silicon, gallium arsenide) substrate 10 of N-type conductivity, forming the bottom gate of the device, into a top surface portion 11 of which respective P-type drain and source regions 15 and 16 are formed. Drain and source contact regions 17 and 18 of high impurity concentration P+ material are introduced into the surface 11 to a prescribed depth in the respective source and drain regions 15 and 16. Overlying the top surface 11 of the substrate 10 is a field oxide layer 25, a relatively thin portion 14 of which lies atop that portion of the substrate into which a top gate region and channel are to be formed. This is shown diagrammatically in FIG. 1 as being disposed between the drain and source regions 15 and 16. Apertures in the field oxide layer 25 are provided for contacting respective drain and source metallizations 23 and 24 to high impurity concentration P+ regions 17 and 18.
The gate/channel structure of the JFET is provided by way of an implanted top gate region 22 of N-type conductivity. Gate region 22 may be formed by implanting suitable N-type conductivity ions, region 22 forming a PN junction 31 with the implanted P material of an underlying channel region 21 and bridging drain region 15 with source region 16. Channel region 21 forms a PN junction 32 with the N material of the substrate. That portion of top gate region 22 which defines a gate-drain PN junction with the P material of drain region 15 is referenced as PN junction 41, an extension of PN junction 31. Also, that portion of top gate region 22 which defines a gate-source PN junction with the P material of source region 16 is referenced as PN junction 42, also an extension of PN junction 31.
In operation, the channel region 21 is normally conductive, so as to provide a current path between the drain and source regions 15 and 16, respectively. In response to the application of a reverse-biasing gate voltage to the top gate 22 and bottom gate (substrate 10), majority charge carriers are depleted from the channel 21. As the space-charge regions extend into the channel, the channel resistance increases, thereby reducing the current between the drain and the source. The top gate is typically tied to the bottom gate with a suitable high impurity concentration (N+) diffused region (not shown).
The breakdown voltage, BV.sub.GSS (drain shorted to source), of an ion-implanted PJFET has been experimentally determined to be modulated by the linear junction gradient of the top gate to channel junction 31. Specifically, junction 31 has a linear grading constant which is a function of top gate implant dosage and implant energy, as well as channel dosage and implant energy. Maintaining a high surface concentration at the top gate/oxide interface 11 limits the freedom to minimize the grading constant of the junction.
One solution to this problem, described in my U.S. Pat. No. 4,683,485, issued Jul. 28, 1987, entitled Technique for Increasing Gate-Drain Breakdown Voltage of Ion-Implanted JFET, assigned to the assignee of the present application, and diagrammatically illustrated in FIG. 2, is to incorporate a high impurity concentration region 62 within top gate region 61 (which has impurity concentration lower than that of region 62). Region 62 is physically separated from source and drain regions 15 and 16 by surface portions 66 and 67 of top gate region 61. Now, although such an improved JFET configuration addresses the condition where the JFET breakdown is limited by the junction gradient of regions 61/15 and/or 61/16, it has been found that such a structure is prone to hot electron degradation at surface portions 66 and 67 of region 61 with oxide/silicon interface 11.
More particularly, in NJFETs implemented with the structure of FIG. 2, the low surface concentration of top gate region 61 (which, in this case, is p-type) tends to facilitate inversion at the surface, due to ionizing radiation-induced positive fixed charge build-up in the oxide layer 14. Such an inversion layer results in a low breakdown voltage and high reverse leakage current.